Anti-fuses are a common component in conventional integrated circuits. An anti-fuse is a circuit element that is normally open circuited until it is programmed at which point the anti-fuse assumes a relatively low resistance. Anti-fuses are commonly used to selectively enable certain features of integrated circuits and to perform repairs of integrated circuits. Repairs of integrated circuits are typically accomplished by "blowing" anti-fuses to signal defective portions of the integrated circuit that they should be replaced with redundant circuits. For example, a defective row of memory cells in the array of a dynamic random access memory can be replaced with a redundant row of cells provided for that purpose.
Conventional anti-fuses are similar in construction to capacitors in that they include a pair of conductive plates separated from each other by a dielectric or insulator. Anti-fuses are typically characterized by the nature of the dielectric which may be, for example, oxide or nitride. Anti-fuses are programmed or "blown" by applying a differential voltage between the plates that is sufficient to break down the dielectric thereby causing the plates to contact each other. Typically this relatively high programming voltage is applied to the chip externally through terminals that are normally used for other purposes. For example, in a DRAM, a high voltage may be applied to one of the data bit terminals after the integrated circuit has been placed in a programming mode by, for example, applying a predetermined combination of bits to other terminals of the integrated circuit.
Although conventional anti-fuses as described above have worked well in many applications, they nevertheless have several shortcomings, particularly when used in more recent, high density integrated circuits. In particular, the programmed resistance of anti-fuses varies over a considerable range, and the programmed resistance is often far higher than is desired. For example, sometimes the programmed resistance is high enough that circuitry connected to the anti-fuse mistakenly determines that the anti-fuse is open circuited. It is generally known that programming anti-fuses with a higher voltage will both lower the programmed resistance and provide a more uniform resistance. However, the magnitude of the programming voltage that can be applied to anti-fuses is severely limited by the presence of other circuitry in the integrated circuit. In particular, since the terminals on which the programming voltage is applied are typically used for other functions, excessive programming voltages can easily break down the gate oxide layers of MOSFET's connected to such terminal thereby making such transistors defective. The problem of programming voltages breaking down the gate oxide layer of MOSFET's is exacerbated by the wide range of operating voltages of typical integrated circuits. For example, recent integrated circuits are capable of operating with a supply voltage of 3.3 volts in order to minimize power consumption, but they must still be able to operate with a commonly used supply voltage of 5 volts.
Excessive programming voltages can also exceed the breakdown voltage of bipolar transistors that are connected to the input terminals of integrated circuits to provide electrostatic discharge ("ESD") protection for the remaining components of the integrated circuit. While this problem can be alleviated to some extent by increasing the breakdown voltage of the bipolar ESD protection transistors, doing so reduces the safety margin of the ESD protection. While the problem of breaking down gate oxide layers of MOSFET's and exceeding the breakdown voltage of bipolar ESD protection transistors could be alleviated to some extent by using dedicated terminals to program anti-fuses, the problem would nevertheless remain because it would be difficult to isolate the programming voltage from the integrated circuit substrate. If the programming voltage was coupled to the integrated circuit substrate, excessive voltages could still be coupled across the gate oxide layers of MOSFET's, even though the programming voltage was not applied directly to the gates of the transistors.
A conventional circuit 10 for programming and reading the state of an anti-fuse is illustrated in FIG. 1. As shown in FIG. 1, an anti-fuse 12 is in the form of an NMOS transistor 12 having its gate connected to the circuit ground CGRN input and its source and drain connected to each other. However, other varieties of anti-fuses, such as parallel plates separated by a dielectric, may also be programmed and read using the circuit shown in FIG. 1. The circuit 10 also receives an active low programming input PRG* and an active low address match input AM* which are applied to the inputs of a NOR gate 14. The output of the NOR gate 14 is applied to the gate of an NMOS transistor 16 which is connected between ground and the anti-fuse 12 through an NMOS transistor 18. The gate of the NMOS transistor 18 is biased to the supply voltage so that the NMOS transistor 18 is conductive whenever the NMOS transistor 16 is conductive. However, during normal operation PRG* and/or AM* are high thus turning off the NMOS transistor 16 to effectively isolate the anti-fuse from ground.
In normal operation, the circuit ground CGRN input is connected to ground. The status of the anti-fuse 12 is read by inputting a high fuse read "FR" input to an NMOS transistor 30. The drain of the NMOS transistor 30 is connected to the drain of a PMOS transistor 32 which is biased on so that it essentially acts as a resistor connected between the supply voltage and the drain of the NMOS transistor 30. Thus, when the fuse read FR input goes high, the NMOS transistor 30 applies the supply voltage to the anti-fuse 12 through the PMOS transistor 32. The PMOS transistor 32 and the anti-fuse 12 thus essentially form a voltage divider having an output at the drain of the PMOS transistor 32 which is connected to the input of an inverter 40.
The channel length to width ratio of the PMOS transistor 32 is selected so that, when the anti-fuse 12 is blown, a low logic level will be applied to the input of the inverter 40. Conversely, when the anti-fuse 12 is not blown, a high logic level will be applied to the input of the inverter 40. The FOUT output of the inverter 40 thus provides an indication of the state of the anti-fuse 12 when a high fuse read FR input is applied to the circuit 10.
When the anti-fuse 12 is to be programmed, the program PRG* and address match AM* inputs both go low thereby causing the NOR gate 14 to output a logic high. This logic high turns on the NMOS transistor 16 thereby grounding through NMOS transistor 18 the plate of the anti-fuse 12 formed by the source and drain of the NMOS transistor. A positive voltage is then applied to the circuit ground CGRN input thereby placing a voltage across the anti-fuse 12 equal to the value of the programming voltage applied to the circuit ground CGRN input.
It will be understood that the prior art circuitry shown in FIG. 1 is integrated into additional circuitry that interfaces with the anti-fuse 12. However, this additional circuitry has been omitted for purposes of brevity and clarity.
The principal disadvantage of the prior art circuit 10 shown in FIG. 1 is that the differential voltage across the anti-fuse 12 is limited to the value of the programming voltage applied to the circuit ground CGRN input. If the programming voltage is increased sufficiently to consistently program the anti-fuse 12 to a relatively low resistance, the programming voltage may very well break down the gate oxide layer of MOSFET's (not shown) in the integrated circuit or make exceed the breakdown voltage of bipolar electrostatic discharge protection ("ESD") transistors thereby causing transistors to limit the programming voltage to the snap back voltage of the ESD transistors.
There is therefore a need for a method and apparatus for programming anti-fuses with a relatively high voltage in a manner that does not damage other components in an integrated circuit.